IPOntellectualPIDperty) is a new concept proposed with the development of EDA (ElectroniDesignAn-tomaTIon) technology. With the rapid revolution in the microelectronics industry, the design of integrated circuits is becoming larger and larger to meet the needs of increasingly complex electronic systems, and at the same time due to the requirements of the time-to-market linetoMarket, it is necessary to spend as little time as possible to prove the components. And system reliability. Therefore, from the perspective of sharing, the reuse of functional modules that have been designed and verified is undoubtedly the best solution to this bottleneck.
The current design idea is a software-like object-oriented concept that uses the concept of virtual socket VS (VirtuaS0ckets) to combine circuit modules from different sources to achieve the required functions and integrate them on a single piece of silicon. IP is the best way to implement the mixing, matching and reuse of this functional module to implement the system-on-a-chip (SystemonACh ring design). This will make system-level IC integration design a practical technical direction.
IP is essentially a functional module that provides the correct interface signal. The definition of MentorGraPhics is a reusable component (ReusableComPOnentS). Specifically in the ASIC/IC design, it usually refers to a soft core, which is a functional module verified by a specific circuit (Silicon-Verified). It is given in the synthesizable register transfer level RWRegisterTranslaTIonbevel) file, which can be called by the library file. Achieve its reuse.
2, programmable DMA controllerThe DMA direct memory access processor is a peripheral interface circuit chip for a microprocessor system. It enhances data throughput by enhancing the performance of information transfer between the system's external devices and main memory.
The 8237A is an 8-bit DMA controller from Intel that offers a wide range of programmable control features while allowing the program to be dynamically programmed to optimize the system. It mainly works with the microcontroller to perform a large amount of high-speed data transfer between the peripheral device and the memory, and it also provides a memory-to-memory transfer function. There are a large number of micro-control circuits using the 8237A as a peripheral interface circuit chip, so the IP design of the 8237A is of great significance for the on-chip integration of these systems.
The 8237A's IP contains the following features:
(1) Contains four channels, each channel can have four working modes, which can be transmitted in single byte, block transmission, and cascade operation. Each channel can be expanded to any channel number by connecting additional controller chips in cascade mode. The other three modes can be programmed by the user to provide DMA transfer services for peripheral devices.
(2) The channel programming is set to auto-initialization, and the channel can be initialized automatically whenever the transfer is finished or the EOP signal is valid. Since each channel's address and word register are 16 bits, it has a 64K address and word count capability.
(3) Provide channel priority control for fixed and cyclic priority scheduling. The most prominent feature of the 8237A is its control over multiple transmission methods.
3, circuit function module designThe entire system is designed to be a fully synchronous circuit. According to the device timing provided by Intel, the design flips the state on the falling edge of the system clock CLK to give the corresponding control signal; and the data channel of the system transfers data on the rising edge of the system clock CLK. Through the logic analysis between the documents, the designed IP circuit is divided into the following modules: interface module, channel request priority and mask control module. Central control module, channel address and counter control module, command register module, status register module. Figure 1.
The main function of the interface circuit is to achieve connection to the CPU and memory as well as external devices. Receives the command word, address, number of bytes, mode control rate, etc. written by the CPU; provides the status word and the contents of each register to the CPU. The interface to the memory and peripherals generally provides the current address for transferring data. In the memory-to-memory transfer mode of operation, the transmitted data is also temporarily stored using the temporary register Temp.
3.2 channel please priority and shield control moduleThis module uses the edge detector and or logic to implement the edge trigger and level trigger detection of DREQ (DMARequest). At the same time, it determines whether the corresponding request is valid through the setting of priority setting and mask register, and then sends a valid request. The central control module, the central control module processes the corresponding channel, and sends a DACK (DMAcknowle eats the small response signal to notify the peripheral to cancel the DREQ request. The priority can be set to fixed priority and cyclic priority by command mode.
3.3 Central Control ModuleThis is the core part of the entire IP design. The module acts as the main working module of the DMA controller and executes various control commands accordingly. It is responsible for idle (id is responded to by the CPU in cycles; during execution (AcTIVe timing, coordination within the DMA) The other modules take over the bus control, provide all the address and data temporary storage control required for data transmission, and provide read and write timing signals to the outside.
The working process of the 8237A can be divided into seven states, namely SI, SO, S1, S2, S3, S4 and Sw. Its state transition is shown in Figure 2. The main component of the module is the system state machine, and the reference, SZ, S4 state performs the main operation on the data channel, and the 8237A is a synchronous circuit, so the central control module is designed as a synchronous state machine, each state is The width of one clock cycle.
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