DC (Design Compiler) is Synopsys's logical synthesis optimization tool that automatically synthesizes an optimized gate-level circuit based on the design descripTIon and constraints. It can accept a variety of input formats, such as hardware description languages, schematics, and netlists, and generate a variety of performance reports to improve design performance while reducing design time.
1.2 How many input formats can DC accept?
Supports .db, .v, .vhd, edif, .vgh, etc., as well as .lib and other related formats.
1.3 How many output formats does DC provide?
Provide .db, .v, .vhd, edif, .vgh, etc., and output sdc, .sdf and other related format files.
What is the main function or main function of 1.4 DC?
DC is a gate-level circuit that integrates circuits described in HDL into process-related circuits. And according to the user's design requirements, the best results are achieved in TIming, area, TIming and power. Return DC for timing verification after floorplanning and placement and inserting the clock tree
1.5 How to find help?
There are 3 ways to help with help:
1. Use SOLD to find answers in your document
2. Use the man+ DC command on the command line
3. Use the info+ DC command on the command line
1.6 How to find SOLD documents?
The SOLD document can be entered in teminal as Sold & Execute.
$" sold&
Or use the command which dc_shell to find the dc installation directory. Find the online directory.
1.7 How to configure DC?
Comprehensive settings provide the necessary parameters to the DC so that the tool can know the necessary information needed for synthesis, ie important parameters: process library, target library, logo library, and so on. Set these parameters on .synopsys_dc.setup. The .synopsys_dc.setup is described in three directories. One is the synopsys installation directory, one is the user folder, and the last is the project directory. The previous file is overwritten by the latter setting.
Parameters include: search_path, target_library, link_library, symbol_library
What does 1.8 target_library mean?
Target_library is the actual technology library needed for the synthesis map
1.9 link_library how to specify?
The library needed for linking is usually the same as the library. When setting, you need to add "*" to indicate all the libraries in the memory.
1.10 search_path settings?
This parameter specifies the storage location of the library
1.11 What is the difference between DA and DC?
DA is short for Design Analyzer. It calls dc for synthesis. But it is graphical. You can see the logic circuit diagram, of course, your library has a symbol library.
1.12 Why use DA instead of shell interface?
For the time being I don’t know the answer
1.13 What is SOLD?
SOLD is an abbreviation of Synopsys OnLine Document and basically includes a collection of documents of all tools of synopsys.
1.14. What DC command is used to translaTIon this step?
We know that the DC synthesis process includes three steps: translation + logic optimization + mapping
The corresponding command for transition is read_verilog(read_vhdl, etc.)
Logic optimization and mapping correspond to compile
1.15. What are the DC commands for logic optimization and mapping?
Logical optimizations and mappings are done in the compile command, but special optimizations can be specified: structural and flatten
1.16. What is a DC script?
DC script. is a collection of dc commands. Make the integration process can also be easy to manage.
1.17. What is the meaning of path-based synthesis?
The path is an important concept in DC. It includes 4 ways of routing:
a. input to the FF data port;
b. Clk of FF to D port of another FF;
c. FF clk to output port DICDER
d. input to output
Path-based synthesis imposes constraints on these four paths and integrates circuits to meet these constraints.
How is the unit of various parameters in 1.18 DC determined?
The unit of the parameter is determined by the library file used. After reading the library, you can use the report_lib to view the information of the library. There are detailed unit descriptions.
What are the objects in the 1.19 DC?
Design variables: There are eight types: Design, cell, reference, port, pin, net, clock, and library. Among them, the cell is the instantiation of the sub-design, the reference is the generic name of multiple sub-design instantiations, the port is the input/output of the design, and the pin is the input/output of the cell.
1.20 What is start point and end point?
These two concepts are the starting point and the ending point of the path concept in DC.
The starting point can be clk for input and FF
The end point can be FF data and output.
1.21 How to find the object that you want to constrain?
One is all lookups include: all_inputs, all_outputs, all_clocks, all_registers. One is based on keywords to find: find_ports(), find(port,' ').
1.22 What is a design?
Design is an important object in DC. What you want to synthesize is called design, or exactly what you want to synthesize the top file of the module.
1.23 What is a cell?
In design, the child design of an instance is called a cell.
What does 1.24 reference mean? What is the difference between cell and cell?
When a module is instantiated multiple times, the module is called reference
1.25 How to read in a design?
Use the analyze + prepared or read_verilog, read_vhdl, read_file commands.
1.26 analyze+indicate what is the difference between the read command and the read command?
Read_file can read any of the SYNOPSYS support formats; analyze and eloborate only support verilog and VHDL formats, but they support the addition of parameters in the middle and can be used to speed up the read process later.
1.27 How to deal with multiple references?
One way is to use uniquify, which is to refer to several times and then rename it in memory to introduce multiple sub-designs for different timing constraints. You can also use the dont_touch command to compile multiple referenced designs before setting dont_touch. It applies to basically the same environmental requirements; another is to flatten the two references and then synthesize them.
What is the role of 1.28 link?
Determine if all files exist and link them to the current design.
1.29 What does the environment setup mean?
Refers to the physical parameters of the chip, such as voltage, temperature, etc.
1.30 How to set up an onboard model?
Use the set_wire_model command
1.31 How to know the type of line model?
Read the library file to DC, use report_lib to see how many available on-line models
1.32 How to set working environment variables?
Use set_operating_conditions
1.33 What kinds of categories can be classified into working environment variables?
It can be generally divided into worst case, typical case and best case.
1.34 Why set working environment variables?
Since we need to do a chip that is to work properly in a real environment, and the performance of the circuit under different temperatures and environments has a great influence, so to properly simulate the chip work, set the appropriate working environment information It is very necessary.
What did 1.35 read and analyze + ealborate do?
Grammar check, establishment of GETECH library. It is worth noting that the read command does not automatically perform the link operation.
1.36 What is the use of the getech library?
The GETCH library is composed of soft macros, adders, multipliers, and the like. These components are referenced in the DW.
1.37 After calling the adder in the getech library, how do you choose the adder that a designer needs?
There is no answer
1.38 Can I swap different adders in the optimization stage after I call the adder?
There is no answer
1.39 How to check the script file for any errors?
Dc_shell -tcl -f
1.40 What if I want to modify the library after dc_shell starts?
There is no answer
1.41 How to Execute UNIX Commands in the dc_shell Environment?
1.42 optimization is divided into several levels?
One is based on HDL structure optimization into GETCH structure; based on GTECH logic optimization, including the framework (strcuture), flatten (flatten), transformed into optimized GETCH; GECH-based gate-level optimization, the main role is to map to the actual Technology library.
1.43 What is a constraint?
The constraints are divided into design constraint and optimization constraint. The design constraint is not determined by the user and has been determined by the library used, and the user can only add further constraints. Optimization constraint is divided into two aspects, timing constraints and area constraints. The timing constraint can be further divided into the constraints of the combinational circuit, the constraints of the sequential circuit, and the constraints of the input and output.
1.44 Does DC Script support TCL?
Dcsh and dc-tcl. The former is the internal language of SYNOPSYS, and the latter is TOOL COMMAND language (TCL).
1.45 What should I do if I do not want to use some library units for mapping?
Use the set_dont_use command
/******** Part 2 Compile stategy **************/
2.1 Constraints A design is divided into several aspects?The total is divided into area constraints and timing constraints.
2.2 What is the area constraint command?
Set_max_area
2.3 How to constrain the clock?
Constraining the clock is to describe the clock cycle and waveform.
Create clock constraints using create_clock
2.4 How to constrain pll?
If there is a PLL, the input's initial clock is first constrained with create_clock.
The create_propagated_clock is then used to constrain the PLL output clock based on the input clock.
2.5 What is a virtual clock constraint?
The virtual clock refers to the physical clock that does not exist in the module that is currently integrated. For example, the clock of the DFF outside the design.
Establishing such a clock is useful for describing the constraint relationship between asynchronous circuits.
2.6 What characteristics of the clock can be controlled by the DC?
DC support for clock cycles, waveforms, jitter, skew, latency
2.7 How to Constrain Clock's Jitter?
Use the set_clock_uncertainty -setup(-hold) constraint clock jitter
2.8 How to Constrain Skew of a Clock?
Use the set_clock_uncertainty to constrain the skew of the clock network
2.9 How to Constrain the Clock's latency?
Use set_clock_latency -option, option is source or network, the default is network.
2.10 How to constrain the external conditions of the currently designed port?
The external conditions of the port include input driver size, output load size, and fanout size.
2.11 How large is the input port driven?
You can use set_dirive and set_driving_cell
2.12 How much load does the output port drive?
Use set_load to constrain the value of the output capacitor in units of the definition of the technology library.
2.13 DC is based on the synthesis of the path, then how to reflect the constraints?
We know that there are four paths based on the path, provided in the DC
Create_clock defines the path between registers and registers;
Set_input_delay defines the path between the input and register;
Set_output_delay defines the path between the register and output;
Set_max_delay and set_min_delay define the combined path of input and output;
What is the purpose of 2.14 set_input_delay?
Define the input delay to constrain the timing of the input logic in the design
What is the purpose of 2.15 set_output_delay?
Defining the output delay to constrain the timing of the output logic in the design
2.16 How to constrain a combinational circuit?
Combination circuit has set_max_delay and set_min_delay to constrain
2.17 How to constrain the circuit speed?
Constrain the speed of the circuit by constraining the circuit clock cycle, using create_clock
2.18 What happens when a combinational circuit exceeds the clock period constraint?
If you must meet the clock cycle constraints, you must modify the design, if it is not strictly required, you can set_false_path can escape path check.
2.19 How to constrain the circuit when a loop circuit appears?
Use set_false_path for a path
2.20 How to Strengthen the Design Rules?
DRC is the design rule that the circuit must meet, use
Set_max_capcitance
Set_max_fanout
Set_max_tansition
2.21 How do I remove constraints for certain paths after adding four path constraints?
Use set_flase_path so that some paths do not perform timing check
2.22 For some paths that need to be completed within a fixed number of cycles, how do you constrain these paths?
Constrain the path using set_multicycle_path
2.23 How to restore the original common timing constraint after adding these special path constraints?
Use reset_path
2.24 How to Constrain Tri-State Gates?
Since the default three-state gate is enable during synthesis, set_false_path must be set for some paths.
2.25 How do I constrain the gated clock to ensure normal operation?
Set up and hold checks on gated clock circuits using set_gating_clock_check
2.26 What should I do when I set some operations such as adding a buffer to a certain network such as clock or reset?
Use set_dont_touch_network
2.27 How to Fix the Hold Time Conflict?
Add the set_fix_hold constraint
/************ Part 3 Compile stategy ******************/
3.1 How many integrated strategies do you choose to integrate?You can use top-down and bottom-top.
3.2 What are the advantages of the top-down approach?
Only need to provide a single TOP script
Get the design as a whole for better results
3.3 What are the advantages of the bottom-up approach?
More suitable for synthesis of multiple clocks
Each sub-module has its own script for easy management
When a module is changed, there is no need to re-integrate all the designs
3.4 How to perform time-budge?
Use characteristic
What are the disadvantages of 3.5 top-down mode?
Long compilation time
Sub-module changes, the entire design must be re-integrated
Incompetent for multiple clock designs
What are the disadvantages of 3.6 bottom-up mode?
Need to maintain multiple scripts
What does 3.7 compile-incremental mean?
After the design maps to a gate, the timing and area constraints can be redefined, incrementally ensuring that the previous circuit structure is maintained, only improving timing and performance, and not adding unnecessary logic.
3.8. . .
/******* Part 4 Analyze the report ******************/
4.1 How to see the area report?Report_area
4.2 How to see the timing report?
Report_timing
4.3 Want to see the area report for individual units? What command is used?
Report_cell But the default report_cell can only look at the area of ​​the cell below the current_design. So there are two ways to solve this problem:
1. You can see all the cells with report_cell [get_cells -hier *]
2. Use list_design to list all designs, then change current_design to the level you want to see, and use report_cell directly.
4.4 How to look at the design environment and the on-line model?
Report_design
4.5 If the design rules and timing violate the constraints, how to view?
Use report_constraint -all_violators
4.6 How to check the fan-in, fan-out, load, capacitance and transition time of the connection?
Use report_net
4.6 How to see how many types of circuit gates are used in the integrated netlist?
Use report_hierarchy
4.7 How to check timing exceptions for timing exceptions?
Use report_timing_requirements
/****************** Part 5 Output the result ***********/
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