The AD9136 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2800 MSPS and can generate multiple carriers over a wide bandwidth. The DAC output is optimized to interface seamlessly with Analog Devices' ADRF6720 and ADRF670x analog quadrature modulators (AQM). An optional 3-wire or 4-wire serial port interface (SPI) allows programming and readback of many internal parameters. The full-scale output current can be programmed from a typical range of 13.9 mA to 27.0 mA. The AD9136 is available in an 88-lead LFCSP package.
AD9136 product features:
1. Ultra-wide complex signal bandwidth above 2 GHz to support emerging broadband and multi-band wireless applications.
2, advanced low spurious and distortion design technology, broadband signal from baseband to high intermediate frequency can achieve high quality synthesis.
3. JESD204B subclass 1 supports simplified multi-chip synchronization in software and hardware design.
4. For data interface widths with serializer/deserializer (SERDES) JESD204B 8-channel interface, fewer pins.
5. The programmable transmit enable function achieves a design balance between power consumption and wake-up time.
AD9136 application:
1, wireless communication
2, 3G/4G W-CDMA base station
3, broadband repeater
4. Software Defined Radio
5, broadband communication point-to-point local multi-point distribution service (LMDS), and multi-channel multi-point distribution service (MMDS) transmit diversity, multiple input / multiple output
Internal function diagram of AD9136:
Figure 1: Internal Functional Diagram of the AD9136
The AD9136 synthesizer analog application block diagram:
Figure 2: Block Diagram of the Analog Application for the AD9136 Synthesizer
The independent SERDES PLL implements clock synthesis using integer-N divide-by-frequency techniques. The SERDES PLLs are all integrated on-chip, including VCO and loop filters. The SERDES PLL VCO operates from 5.65 GHz to 12 GHz. In the SERDES PLL, the VCO divider block divides the VCO clock by 2 to produce the 2.83 GHz to 5.52 GHz quadrature clock used by the deserializer core. This clock is the clock and data recovery module described in the "Clock and Data Recovery" section.
AD9136/AD9135 Datasheet: Download Now
More schematics and PCB code:
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