ARM microcontroller is the entry point for most newcomers to choose, but due to lack of knowledge, novices often encounter such problems during the design process. ARM abnormal interrupt return is such a headache. Abnormal interrupt return in the use of ARM is a problem that novices are more annoyed. This article will summarize the concentration of ARM abort and give some solutions.
Before the formal introduction, we must add some more important basic knowledge. First, R15 (PC) always points to the "fetching" instruction, not to the "executing" instruction or the "decoding" instruction. In general, people habitually agree to "the instruction being executed as a reference point", which is called the current first instruction, so the PC always points to the third instruction. When the ARM state, each instruction is 4 bytes long, so the PC always points to the address of the instruction plus 8 bytes of address, ie: PC value = current program execution position +8; and the PC in ADS is for debugging Convenient and modified, it points to the instruction being executed, that is, "true pc-8"!
SWI and undefined instruction aborted return
Instruction address:
A PC-8 current command is SWI or undefined instruction. At this time, the interrupt occurs. The value of PC has not been updated.
The processor saves PC-4 to the LR when the A+4 PC-4 is interrupted. ;r!
A+8 PC
On return, the execution starts from the next instruction A+4 (PC-4) of the interrupt A (PC-8), so the value of LR is directly assigned to the PC. The specific instruction is MOV PC, LR ( PC = A + 4 = LR).
Vernacular explanation: PC does not update when an abnormality occurs in SWI and undefined instructions. According to ARM's three-stage pipeline principle, pc is not updated, still equal to (A+8); lr = pc – 4 (at this time, the processor determines that it cannot Change !) ie A+4.
Since the next instruction (A+4) should be executed after such an exception is returned, pc=lr can be returned.
The return instruction address of IRQ and FIQ abnormal interrupt processing corresponds to PC A. After PC-8 executes this instruction (!), it queries IRQ and FIQ, and if there is an interrupt request, it generates an interrupt.
A+4 PC-4
A+8 PC ;lr!
(At this point, the value of the PC has been updated, pointing to A+12. The current PC-4, ie A+8).
Save to LR. When returning, the instruction at A+4 (LR-4) is executed, so the return instruction is:
SUBS PC, LR, #4 (PC=A+4=LR-4)
Vernacular explanation: For general interrupts and fast interrupt exceptions, the interrupt must be detected after an instruction is executed. If an interrupt occurs while executing the instruction A, the interrupt will not be processed after the instruction is executed. When an exception occurs. Pc has been updated (A+12); lr=pc– 4 (when the processor decides, cannot be changed!) After A+8 returns, it should execute the interrupted command without execution (A+4 above). So when returning, pc=lr-4.
Instruction prefetch aborts the return of abnormal interrupt processing
Instruction address:
A PC-8 An interrupt occurs while executing this instruction. The A+4 PC-4 processor saves A+4 (PC-4) to:
LR. ;lr! A+8 PC
On return, the instruction A (PC-8) where the instruction prefetch abort occurs is re-executed, so the return instruction is SUBS PC, LR, #4 (PC = A = LR-4).
Vernacular explanation: When the prefetch instruction abort exception occurs, the prefetch instruction exception is an exception that occurs during execution. The pc is not updated, that is, pc=A+8; lr=pc – 4 (when the processor decides, it cannot be changed. !) is A+4.
Since this type of exception should be re-executed after the exception is returned (A), when returning, pc = lr-4.
Data access aborted exception interrupt processing return
Instruction address:
A PC-8 This instruction accesses the problematic data. When an interrupt occurs, the value of the PC has been updated.
A+4 PC-4 interrupt occurs when PC=A+12, and the processor saves A+8 (PC-4) to LR.
A+8 PC ;lr!
When returning, return to A to continue execution, so the instruction is SUBS PC, LR, #8. (PC=A=LR-8)
Vernacular explanation: When data access aborts an exception, it is accessing data errors during execution.
The resulting exception, pc has been updated, that is, pc = A + 12.
Lr=pc–4 (when the processor decides, it cannot be changed!) is A+8.
Since this type of exception should be re-executed after the exception is returned (A), when returning, pc=lr-8.
to sum up
One reason for the PC update is that the data is aborted and there is an interruption.
The interrupt must be detected after an instruction has been executed, so it breaks only the one that has not yet been executed. Command (pc-8), so pc=lr – 4;
Like interrupts, SWI and undefined instruction exceptions also return to the next instruction (pc-4), except that when they are executed, the value of the PC is not updated, so pc=lr.
The prefetch instruction aborts the exception, and no pc update occurs, but it has to re-execute the instruction that the exception occurred, so pc=lr–4.
The data access aborts the exception, a pc update occurs, and it also needs to re-execute the instruction that the exception occurred, so pc=lr–8.
Through the above introduction, we can see that there are many reasons for the return of the MCU interrupt, and the solution for each method is different. A friend who encounters an interrupt return problem during the debugging of the ARM chip may wish to read this article carefully, and I believe that the solution to the problem will be found. You can also collect this article in case you need it, and check it when you encounter an error.
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