I know that I'm fascinated by all things related to electronics, but from what point of view, today's Field Programmable Gate Arrays (FPGAs) seem to stand out from the crowd and are really great devices. If in this intelligent era, in this field, you want to have a skill you have not paid attention to FPGA, then the world will abandon you and the era will abandon you.
Use hard cores as much as possible, such as hardware multipliers, which should all be known.
The structural pipeline, in short, is “demolitionâ€. The most extreme situation is that there are only basic combinatorial logic gates between the source and the destination Reg, such as ~a & b, and so on. Of course, this is not necessary in FPGAs. For example, two xbit data are compared. If there is a 4-input LUT in the chip, if the pipeline is necessary, the flow level can be up to [log4(x)]+1.
Water flow on the system, that is, shooting, side effects are brought latency; This is one of the most common ways, but in some cases it is not allowed.
Asynchronous division of different clock domains; for example, the system body can work at 100M-, specific subsystem requirements must work at 300M+, then you can divide specific modules into different clock domains; but the asynchronous clock domain should not be too much.
When synthetically using retiming, duplication; physical synthesis optimization, the current synthesizer is smart enough.
The budget allows the use of faster chips; this may be the most likely way to achieve "without modifying RTL and timing closure."
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