EMC design of automotive electronics
Automotive electronics is in a noisy environment, so automotive electronics must have excellent electromagnetic compatibility (EMC) performance. The most important thing in the EMC design of automotive electronics is the design of the microprocessor. The author will combine the actual design experience to analyze the generation mechanism of noise and propose a method to eliminate noise.
Automotive electronics often work in harsh environments: the ambient temperature range is -40oC to 125oC; vibration and shock often occur; there are many noise sources, such as wiper motors, fuel pumps, spark ignition coils, air conditioner starters, and alternator cables Intermittent disconnection of the connection, and certain wireless electronic devices, such as mobile phones and pagers.
Automobile design generally has a highly integrated microcontroller, which is used to complete a large number of calculations and realize the control of vehicle operation, including engine management and brake control. Automotive electronics design not only needs to protect the MCU in this noisy environment, but also must standardize the MCU module design to ensure that the noise emitted by the MCU module meets the relevant specifications.
Conceptually, electromagnetic compatibility (EMC) includes the system's own sensitivity to noise and noise emission. Noise can propagate through electromagnetic fields to produce radiated interference, or it can be conducted through parasitic effects on or off the chip.
EMC is becoming more and more important in the design of most automotive control systems. If the designed system does not interfere with other systems, nor is it affected by emissions from other systems, and does not interfere with the system itself, then the designed system is electromagnetically compatible.
Any electronic equipment and systems sold in the United States must comply with the EMC standards set by the Federal Communications Commission (FCC), and major automakers in the United States also have their own set of test specifications to restrict their suppliers. Other car companies usually have their own requirements, such as:
SAE J1113 (Automotive Device Electromagnetic Susceptibility Test Procedure) gives the recommended test levels and test procedures for automotive devices.
SAE J 1338 provides information on how to test the electromagnetic sensitivity of the entire car.
SAE J1752 / 3 and the second and fourth parts of IEC 61967 are two standards dedicated to IC emission testing.
Europe also has its own standards. The European Union EMC Directive 89/336 / EEC came into effect in 1996. Since then, the European automotive industry has introduced a new EMC guideline (95/54 / EEC).
Check the sensitivity of the car to electromagnetic radiation. It should be ensured that the reference level of the entire car is limited to the rms value of 24V / m within the 90% bandwidth of 20 to 1000MHz, and the rms value within the entire bandwidth is 20V / M within. During the test, it is necessary to test the driver's direct control of the steering wheel, brakes, and engine speed, and no abnormalities that may cause confusion to anyone else on the road surface or abnormalities that the driver directly controls the car are allowed.
As the chip geometry continues to decrease and the clock speed continues to increase, the device will emit clock harmonics exceeding 500MHz, so EMC design is very important. For example, Motorola's latest MPC5500 series microcontroller based on e500 architecture, the chip uses 0.1 micron process technology, the clock frequency is 200MHz.
In addition, product cost requirements force manufacturers to design circuit boards without using ground planes and minimize the number of devices. Automotive design engineers will face very strict design constraints. The electronic system must be designed to be highly reliable, even if one of the million cars has a simple failure. The fact that all cars are recalled without considering the EMC design proves that this approach not only causes huge losses, but also affects the reputation of car manufacturers.
In EMC design, the concept of "victim" usually refers to those components that are affected by the design's lack of EMC considerations. The victim component may be inside the MCU-based PCB or module, or it may be an external system. The usual victim parts are the broadband receiver in the keyless-entry module of the car or the receiver of the garage door opening device. Due to the strong enough noise from the MCU, the receiver in these modules will be wrong. Think that a remote control signal has been received.
Car radios are also often affected components: MCUs may generate a large number of FM band harmonics, severely degrading sound quality. Other modules distributed in the car may also be similarly affected. The emission noise generated by the MCU-based module is propagated through the cable. If the MCU generates enough noise to interfere with text and voice, then the cordless phone and pager are also vulnerable to interference.
EMC design
Many EMC design techniques can be applied to circuit board and SoC design. The most common part is the transmission line effect, as well as the parasitic resistance, capacitance and inductance effects on the wiring and power distribution network. Of course, there are many technologies related to the chip itself in SoC design, including substrate materials, device geometry and packaging.
First understand the transmission line effect. If there is an impedance mismatch between the transmitter and the receiver, the signal will be reflected and cause voltage ringing, thus reducing the noise margin, increasing signal crosstalk and generating signal emission interference through capacitive coupling. The size of the transmission line on the IC is usually very small, so it will not emit noise or be affected by radiated noise. The transmission line size on the circuit board is usually large, which is prone to this problem. The most common solution is to use a series terminator.
In SoC design, noise is mainly conducted through parasitic resistance and capacitance, rather than radiating in the form of electromagnetic fields. The CMOS chip uses an epitaxial process to achieve a very low resistance substrate to enhance the ability to resist latch-up. The bottom side of the substrate provides an effective conduction path for the substrate noise, making it difficult to electrically connect the noise source to sensitive nodes. Separated.
Many parallel p + substrate contacts provide a low impedance path for resistively coupled noise. Parasitic capacitance is formed between the side walls and bottom of the n-well and p-channel transistor p substrate, thus generating capacitive coupling noise, and forming a pn junction between the substrate and source region of the n-channel transistor (see Figure 1) .
The capacitance of a single pn junction is very small. In a VLSI SoC design, the total capacitance in parallel is usually several nanofarads. Directly connecting the source region and the substrate before connecting to the power supply network can short this capacitor. This technique also eliminates the body effect caused by the instantaneous negative current entering the substrate. The body effect increases the depletion region and causes the Vt of the transistor to become higher. The same technique can also be applied to n-well p-channel transistors to reduce capacitive coupling noise.
However, digital circuits or analog circuits containing stacked transistors usually require isolated source regions. In this case, increasing the capacitance of Vss to the substrate or Vdd to the substrate can reduce the noise transient value. For analog circuit design, body effects reduce circuit performance by changing the bias current and signal bandwidth, so other Solutions, such as well isolation, are required. For digital circuits, the use of a single well is ideal, which can reduce the chip area. Through careful design, body effects can be compensated.
Another source of background noise is impact-ionization current. This noise is related to the process technology. This happens when the NMOS transistor reaches the pinch-off voltage. Impact ionization will generate a hole current (positive instantaneous current) on the substrate.
Generally, the frequency range of the floor noise may be as high as 1 GHz, so the skin effect must be considered. The skin effect is to guide the inductance of the body to increase with depth, reaching the maximum value at the center of the conductor. The skin effect will cause the attenuation of the on-chip signal and the distortion of the signal at the chip p + base layer. To minimize the skin effect, the thickness of the substrate is required to be less than 150 microns, which is much smaller than the minimum mechanical thickness allowed by some substrates, however thinner substrates are more fragile.
Noise source
There are four main sources of noise inside the microcontroller: internal bus and node synchronous switch power and ground current; output pin signal conversion; oscillator operation noise; switch capacitor load on-chip signal artifacts .
Many design methods can reduce synchronous switching noise (SSN). Penetration current is a major source of SSN. All clock drivers, bus drivers, and output pin drivers may be affected by this effect. This effect occurs in a complementary type of inverter. When the output state changes, the p-channel transistor and the n-channel transistor are turned on at the same time. Make sure to turn off the other transistor before the complementary transistor is turned on to achieve the minimum penetration current. In the design of high current drivers, this may require a pre-driver to control the conversion rate of the node signal.
SSN can also be reduced by cutting off the clock that does not require the module. Obviously, this technology is very relevant to specific applications, the application of this technology can improve EMC performance. In highly integrated microcontroller chips like Motorola's MPC555 and 565, all the peripheral modules of the chip have such functions.
SSN will also produce radiated interference, instantaneous power and ground current will flow to the external decoupling capacitor through the device pin. If the loop formed by this circuit (including bonding wires, package leads, and PCB wires) is large enough, signal emission will occur. The parasitic inductance in the loop will cause a voltage drop, which will further cause common-mode radiation interference.
The intensity of the common-mode radiated electric field E is calculated by the following equation:
E = 1.26 x 10-6 Iw fl / d
E = 1.26 x 10-6 Iw fl / d
Here the unit of E is volts / meter, the unit of Iw is ampere, f is the unit of hertz, l is the path length, d is the distance to the path, and the units of l and d are both meters. The frequency in a complex design is determined by specific application requirements and cannot be reduced, so SoC design engineers must carefully consider how to reduce the electric field strength by reducing Iw or l.
Handling the clock domain can also reduce SSN. Many excellent SoC designs are synchronous circuits, so it is easy to generate a large peak current at the upper and lower edges of the clock. Distribute the clock driver throughout the chip instead of using a large driver, so that the transient current can be distributed. Another possible solution is to ensure that the clocks do not overlap each other. Of course, care must be taken to avoid competition due to timing mismatch. More importantly, the clock signal should be away from sensitive I / O logic signals, especially analog circuits.
Current complex embedded MCUs have many output signals, and most of the output signals must be able to respond quickly to capacitive loads. These signals include clock, data, address, and high-frequency serial communication signals. For internal nodes, both penetration current and capacitive load generate noise. Applying the same technique to internal nodes can solve the noise problem of the output pin driver circuit. In addition, the rapid change of the signal on the pin will cause signal ringing and crosstalk on the output signal line caused by reflection.
There are many solutions to minimize this type of noise source. The output driver can be designed so that the driving strength can be controlled, and the signal slew rate control circuit can be added to limit the di / dt. Since most device test equipment has higher test node capacitance than the final application, it is usually more willing to specify a fixed value to control the drive strength. For example, assume that the CLKOUT full drive strength of the MPC5XX series of MCU microcontroller chips is a 90pF load, and is specifically set for testing purposes. In addition to considering full drive strength because of timing, it is best to use reduced drive strength.
The technique described above has a positive effect on noise reduction. As the transient current envelope is extended, the average current will actually increase. Implementing an LVDS physical layer on the chip can also reduce the noise caused by the large transient current on the output pin. This method relies on a differential mode current source to drive a low-impedance external load (Figure 2). The voltage swing is limited to ± 300mV.
The additional pins needed to support this technology can be compensated by reducing the power supply pins. Because this implementation effectively reduces the on-chip transient current, the output driver basically maintains a constant DC current through the power supply, while traditional drivers The transient current in the middle will produce a large voltage swing on the capacitive load.
There are two aspects that affect EMC in oscillator design: the shape of the input and output signal waveforms will have an impact; the ability to spread the spectrum and reduce its narrow-band power through frequency jitter.
Oscillators are essentially analog circuits, so they are more sensitive to process, temperature, voltage, and load effects than digital circuits in SoCs. Using feedback in the form of automatic gain control (AGC) circuits to limit the amplitude of the oscillator signal can eliminate most of these effects. Another alternative implementation of AGC is the dual-mode oscillator, which can be switched between a high-current mode and a low-current mode. In the initial state, the high current mode is used to ensure a short start-up time when the power is turned on, and then the low current mode is switched to ensure the minimum noise.
In an SoC design that integrates a phase-locked loop as part of the oscillator circuit, frequency jitter can be used to change the clock frequency within a very small range, so that as the frequency expands over a range, the basic energy can be reduced. The entire system design must be carefully considered to ensure that the ratio and frequency range of this change will not affect the timing of critical devices in the final application. However, this method cannot be adopted in serial communication widely used in automobiles such as CAN, asynchronous SCI, and timing I / O functions. The switching noise on the chip indicates that it is itself a damped oscillation of the desired signal output, which is the result of the series combination of the inductor and the load capacitance on the chip. For a typical on-chip bus, the load is a long PCB wiring connected to many three-state buffers. The main body of the load is the capacitor, including the gate, pn junction, and interconnect capacitance.
Eliminating inductance or reducing di / dt can reduce or eliminate noise. Only when the noise amplitude is so large that it will cause the wrong switch of the connection node, it is necessary to seriously consider the noise problem in the design.
Reducing sensitivity to external noise sources includes consideration of external devices and internal design. External transient currents can cause two conditions on the pins: voltage changes can cause capacitively coupled currents to enter the device; voltages outside the range of the power supply will eventually conduct the current into the device through a resistive path.
In automotive electronics design, an external RC filter is usually used to limit the transient voltage swing and injected current. Care must be taken to ensure that the value of the external device takes into account the effects of leakage current, especially for analog inputs. It is worth noting that the I / O pins of MCU and peripheral IC are usually up to 200. The extra cost and circuit board space required by this solution make engineers unwilling to adopt it in system design. The best solution is to achieve a high degree of integration on the chip.
Hardware and software technologies can work together to achieve EMC performance requirements. For example, many MCUs have the ability to output internal access on an external bus, which is usually not visible. This method is very useful for debugging, but in some improperly designed systems, external bus contention may occur, thereby increasing the related noise.
In my past work, I encountered a similar problem with incorrect readings of the on-chip A / D converter. The problem seems to be that the noise interferes with the measurement or conversion to some extent. By understanding the hardware structure diagram of the system, it seems that everything is normal from the surface of the input part of the A / D converter, but I noticed that the external EPROM implements decoding in some way, and this decoding method is very special in some ways. Under the circumstances, it may cause bus competition. This competition will not affect any operation of the program, but it will generate enough noise, so there will be occasional errors in A / D conversion. This problem was solved quickly by changing the decoding logic.
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